Applied Materials has made a major breakthrough in the field of chip wiring, driving logic scaling into 3nm and below technology nodes

·Integrate seven process technologies into one system under vacuum conditions, halving the interconnection resistance

· New material engineering solutions improve chip performance and reduce power consumption

·The latest system demonstrates Applied Materials' strategy of becoming a PPACt enablement company™ for customers

June 16, 2021, Santa Clara, California-Applied Materials has introduced a new advanced logic chip wiring process technology that can be scaled down to 3 nanometers and below technology nodes.

Applied Materials' new Endura® Copper Barrier Seed IMS™ solution integrates seven different process technologies into one system under high vacuum conditions, thereby improving chip performance and power consumption.

Although reduced transistor size can improve performance, this has the opposite effect on interconnect wiring: the thinner the interconnect, the greater the resistance, resulting in reduced performance and increased power consumption. From the 7-nanometer node to the 3-nanometer node, if there is no breakthrough in material engineering technology, the interconnection through-hole resistance will increase by 10 times, offsetting the advantage of transistor shrinking.

Applied Materials has developed a new materials engineering solution called Endura® Copper Barrier Seed IMS™. This integrated material solution integrates seven different process technologies of ALD, PVD, CVD, copper reflow, surface treatment, interface engineering, and metrology into one system under high vacuum conditions. Among them, ALD selective deposition replaces ALD conformal deposition, eliminating the original high-resistance barrier layer via the interface. Copper reflow technology is also used in the solution to achieve void-free gap filling in narrow gaps. Through this solution, the resistance of the through-hole contact interface is reduced by 50%, the chip performance and power are improved, and the logic scaling can continue to the node of 3 nanometers and below.

Perab, Senior Vice President of Applied Materials and General Manager of Semiconductor Products Division? 6? 7 Raja said: "Each smartphone chip has tens of billions of copper interconnects, and the power consumption of wiring alone accounts for one-third of the entire chip. Integration of multiple processes under vacuum Technology allows us to redesign materials and structures so that consumers have more powerful and longer-lasting devices. This unique integrated solution is designed to help customers improve performance, power, and area costs."

The Endura Copper Barrier Seed IMS system has now been used by customers in the world's leading logical node foundry production. More information about this system and other logic miniaturization innovations has been discussed at Applied Materials' 2021 Logic Master Class held on June 16th, US time.